1. Field of the Invention
This invention relates to improved methods for forming multiple conductive layers on a semiconductor body by providing planarization between conductive layers.
2. Prior Art
In manufacturing multiple conductive layer semiconductor devices, such as a double-metal integrated circuit chip utilizing VLSI technology, a dielectric layer must be deposited between the conductive layers to provide insulation for the conductive layers. Prior art methods have implemented the use of a variety of materials and thicknesses of such materials as dielectric medium between the conductive layers. The topology was not of serious consequence until recently when packaging reached high-density proportions.
A major problem associated with multiple conductive layer depositions was the requirement for a smooth topology for the deposition of a subsequent conductive layer. That is, the dielectric layer needed to fill in the gaps and voids present on the surface of the semiconductor body after the first conductive layer had been patterned and etched so to provide a smooth surface whereupon the subsequent conductive layer could be deposited. As packaging density increased, prior art methods could no longer provide the planarization necessary for consistent reliability. The present invention is directed to the alleviation of defects by providing a planarization process heretofore never been attempted.